Development of semiconductor memory devices has been increasing at a fast pace in recent times because of major breakthroughs in materials, manufacturing processes and designs of semiconductor devices. Semiconductor device manufacturers are constantly enhancing their efforts for more advanced miniaturization, high-integration and capacity increase of the semiconductor devices. This has given an impetus to research and development for more stabilization, higher speeds and smoother operation of semiconductor devices. These results have been brought about by the device makers improving the process techniques, microminiature device techniques and circuit design techniques in the manufacture of semiconductor memory cells such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).
One such advance in the field of SRAM devices has been the development of a dual port SRAM capable of performing a read and write operation at high speeds in place of the conventional single port SRAM. In general, one unit memory cell of a single port SRAM device is composed of six transistors, that is, two load transistors, two drive transistors and two active transistors, to perform the read and write operations sequentially. In contrast, a dual port SRAM device is configured with an addition of two active transistors to the general single port SRAM so as to perform the read and write operations in a dual mode, and which is required to obtain a very high speed operation. However, the dual port SRAM's shortcoming is that the read and write operations interfere with each other to cause a characteristic drop in the semiconductor memory cell since the read and write operations are performed simultaneously.
The layout structure of conventional dual port SRAM will be described next in context of the above-mentioned problems, as follows. FIG. 1 indicates a circuit configuration of dual port SRAM according to the prior art.
Referring to FIG. 1, a single unit of dual port SRAM cell is composed of two load transistors: TL1 and TL2, two drive transistors: TD1 and TD2 and four active transistors: TA1, TA2, TA3 and TA4. First and second load transistors: TL1 and TL2, and first and second drive transistors: TD1 and TD2, are individually connected to form two inverters. The two inverters are cross coupled to create a latch for storing data. A first active transistor TA1 is connected to a read bit line BLR, and a third active transistor TA3 is connected to a write bit line BLW that is positioned adjacently to the read bit line BLR.
A second active transistor TA2 is connected to a complementary read bit line {overscore (BLR)}, and a fourth active transistor TA4 is connected to a complementary write bit line {overscore (BLW)} that is arranged adjacent to the complementary read bit line {overscore (BLR)}. Further, a read word line WLR is shared with the first active transistor TA1 that is connected to the read bit line BLR, and with the second active transistor TA2 connected to the complementary read bit line {overscore (BLR)}. A write word line WLW is shared with the third active transistor TA3 connected to the write bit line BLW and with the fourth active transistor TA4 connected to the complementary write bit line {overscore (BLW)}.
FIG. 2 is a plan view illustrating a layout structure of a conventional dual port SRAM cell. In FIG. 2, the read bit line BLR and the write bit line BLW are adjacently arranged to constitute a bit line pair 20, and the complementary read bit line {overscore (BLR)} and the complementary write bit line {overscore (BLW)} are adjacently arranged to constitute a complementary bit line pair 22.
The dual port SRAM having the above-mentioned configuration performs read and write operations in an independent manner either to write or read data at the same time. This process of reading and writing data is described in detail next.
First, a read operation is discussed. An externally received read address signal is decoded, and according to the decoding result, a word line signal for a read operation is enabled as a logic ‘H’. Next, the first and second active transistors, TA1 and TA2, are turned on, and the data stored at the latch 10 is read through the bit line and the complementary bit line. Similarly, in the write operation, a write address signal is received from the outside and is decoded, and according to the decoding result, a word line signal for a write operation is enabled as a logic ‘H’, and the third and fourth active transistors, TA3 and TA4, are then turned on, and the data loaded on the bit line and the complementary bit line is stored at the latch.
As described above, in a conventional memory structure, a read bit line and a write bit line are adjacent to each other. Further, a complementary read bit line and a complementary write bit line are adjacent to each other. While performing read and write operations, the read operation is influenced by the write operation and the write operation is influenced by the read operation, which means, a cross-talk occurs and brings about a characteristic drop in a dual port SRAM cell. Particularly if the read bit line is adjacent to the write bit line and the complementary read bit line is adjacent to the complementary write bit line, then the problem of crosstalk for read bit line occurs frequently when write operations are carried out.
Further, transistors used in constructing the dual port SRAM cell and individual active regions are not arranged in the same direction, and are positioned distant from one another. Therefore, specific local connection wires are required to connect such distant components. Word lines are also separately configured, and thus require specific local connection wires for a connection between a gate line and a word line and between the respective cells and word lines. Therefore, as the local connection wires for connecting the cell nodes increase, the overall length of wiring increases and also the number of contacts increases simultaneously. Furthermore, the area of circuit layout on a memory chip increases by the increased number of contacts. The increased number of contacts applies a negative influence upon advancing the characteristic features of memory cells.